1. Field of the Invention
This disclosure relates to a method of fabricating a semiconductor device and semiconductor device fabricated thereby and, more particularly, to a method of fabricating an asymmetric source/drain transistor employing a selective epitaxial growth (SEG) layer and asymmetric source/drain transistor fabricated thereby.
2. Description of the Related Art
A semiconductor device generally employs a discrete device such as a MOS transistor as a switching device. As the degree of integration of the semiconductor device increases, the size of the MOS transistor decreases. As a result, the channel length of the MOS transistor decreases to the point that a short channel effect may occur.
Generally, channel ions are doped into the channel region to a high concentration in order to prevent a threshold voltage from decreasing due to the short channel effect. However, when the channel ions are doped to the high concentration, channel resistance increases so that current driving capability is decreased. Also, the increase in concentration of the channel ions leads to an increased electric field between a channel region and source/drain regions. Accordingly, a leakage current between the channel region and the source/drain regions increases. In particular, in a case where a capacitor stores charge, such as when a DRAM cell is connected to a source or a drain, the increase of the leakage current causes degradation of charge retention characteristics.
Methods for preventing the degradation of the charge retention characteristics due to the increase of the electric field between the channel region and the source/drain regions have been widely studied. In particular, methods of fabricating an asymmetric source/drain transistor may be capable of reducing the electric field between the source or drain region to which a capacitor is connected and the channel region while maintaining a constant threshold voltage.
A method of fabricating an asymmetric source/drain transistor appears in U.S. Pat. No. 6,596,594 to Guo entitled “Method for Fabricating Field Effect Transistor (FET) Device with Asymmetric Channel Region and Asymmetric Source and Drain Regions”. According to this method, the asymmetric source/drain regions are formed by performing ion implantation processes.
However, one drawback of forming the asymmetric channel region or the asymmetric source/drain regions with an ion implantation processes is that it is difficult to control impurity ions that diffuse into the channel region.
Embodiments of the invention address these and other disadvantages of the conventional art.